Read e-book online Analog Circuit Design: Low Voltage Low Power; Short Range PDF

By Willy Sansen (auth.), Michiel Steyaert, Arthur van Roermund, Andrea Baschirotto (eds.)

ISBN-10: 9400719256

ISBN-13: 9789400719255

Analog Circuit layout comprises the contribution of 18 tutorials of the twentieth workshop on Advances in Analog Circuit layout. every one half discusses a particular to-date subject on new and worthy layout principles within the sector of analog circuit layout. each one half is gifted by means of six specialists in that box and cutting-edge info is shared and overviewed. This publication is quantity 20 during this profitable sequence of Analog Circuit layout, delivering important info and perfect overviews of:

Topic 1 : Low Voltage Low strength, chairman: Andrea Baschirotto
Topic 2 : brief variety instant Front-Ends, chairman: Arthur van Roermund
Topic three : strength administration and DC-DC, chairman : Michiel Steyaert.
Analog Circuit layout is a necessary reference resource for analog circuit designers and researchers wishing to maintain abreast with the most recent improvement within the box. the academic assurance additionally makes it compatible to be used in a sophisticated layout course.

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Read Online or Download Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC PDF

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Extra resources for Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC

Example text

Singer, A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC. IEEE J. SolidState Circuits 35(3), 318–325 (2000) 36 B. Murmann 14. E. , A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter. IEEE J. Solid-State Circuits 33(12), 1898–1903 (1998) 15. D. , A double-tail latch-type voltage sense amplifier with 18 ps setup C hold time,” in ISSCC Digest of Technical Papers, San Francisco, CA, USA, Feb 2007, pp. 314–605 16. T. Sundstrom, A. Alvandpour, A kick-back reduced comparator for a 4-6-Bit 3-GS/s flash ADC in a 90 nm CMOS process, in Proceedings of the MIXDES, Ciechocinek, Poland, 2007, pp.

IEEE J. Solid-State Circuits 23(6), 1324–1333 (1988) 2 Low-Power Pipelined A/D Conversion 37 39. M. R. 5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter, in Symposium of VLSI Circuits Digest, Honolulu, HI, USA, 1998, pp. 166–169 40. C. A. Hodges, Time interleaved converter arrays. IEEE J. Solid-State Circuits 15(6), 1022–1029 (1980) 41. K. , A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture. IEEE J. Solid-State Circuits 41(12), 2650– 2657 (2006) 42.

One of the first highperformance designs that uses a SHA-less front-end was described by Mehr in 2001 [13]. Today, SHA-less operation is widely used across a wide range of performance specs, even in designs that sample at IF frequencies [34]. The primary issue that must be overcome in a SHA-less design is the clock timing and bandwidth mismatch between signals acquired by the sub-DAC and the main MDAC path. g. g. [35]). For designs with wideband inputs, it is conceivable to measure and calibrate the mismatch [36].

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Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC by Willy Sansen (auth.), Michiel Steyaert, Arthur van Roermund, Andrea Baschirotto (eds.)

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